// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  hipciec_ap_dma_reg_reg_offset_field.h
// Project line  :  Platform And Key Technologies Development
// Department    :  CAD Development Department
// Author        :  xxx
// Version       :  1.0
// Date          :  2017/10/24
// Description   :  The description of xxx project
// Others        :  Generated automatically by nManager V4.2 
// History       :  xxx 2018/03/16 18:03:13 Create file
// ******************************************************************************

#ifndef __HIPCIEC_AP_DMA_REG_REG_OFFSET_FIELD_H__
#define __HIPCIEC_AP_DMA_REG_REG_OFFSET_FIELD_H__

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_L_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_BASE_H_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_DEPTH_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAIL_PTR_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_L_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_BASE_H_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_DEPTH_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_HEAD_PTR_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_0_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_0_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_0_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_0_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_0_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_0_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_0_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_0_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_0_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_0_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_0_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_0_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_0_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_0_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_0_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_0_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_0_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_0_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_0_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_0_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_0_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_0_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_0_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_1_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_1_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_1_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_1_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_1_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_1_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_1_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_1_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_1_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_1_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_1_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_1_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_1_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_1_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_1_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_1_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_1_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_1_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_1_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_1_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_1_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_1_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_1_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_2_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_2_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_2_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_2_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_2_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_2_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_2_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_2_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_2_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_2_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_2_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_2_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_2_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_2_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_2_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_2_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_2_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_2_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_2_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_2_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_2_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_2_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_2_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_3_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_3_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_3_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_3_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_3_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_3_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_3_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_3_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_3_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_3_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_3_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_3_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_3_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_3_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_3_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_3_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_3_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_3_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_3_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_3_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_3_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_3_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_3_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_4_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_4_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_4_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_4_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_4_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_4_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_4_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_4_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_4_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_4_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_4_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_4_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_4_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_4_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_4_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_4_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_4_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_4_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_4_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_4_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_4_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_4_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_4_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_5_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_5_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_5_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_5_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_5_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_5_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_5_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_5_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_5_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_5_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_5_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_5_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_5_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_5_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_5_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_5_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_5_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_5_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_5_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_5_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_5_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_5_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_5_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_6_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_6_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_6_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_6_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_6_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_6_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_6_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_6_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_6_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_6_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_6_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_6_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_6_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_6_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_6_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_6_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_6_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_6_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_6_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_6_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_6_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_6_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_6_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_7_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_7_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_7_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_7_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_7_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_7_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_7_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_7_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_7_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_7_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_7_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_7_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_7_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_7_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_7_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_7_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_7_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_7_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_7_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_7_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_7_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_7_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_7_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_8_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_8_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_8_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_8_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_8_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_8_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_8_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_8_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_8_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_8_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_8_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_8_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_8_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_8_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_8_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_8_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_8_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_8_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_8_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_8_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_8_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_8_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_8_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_9_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_9_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_9_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_9_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_9_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_9_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_9_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_9_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_9_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_9_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_9_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_9_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_9_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_9_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_9_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_9_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_9_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_9_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_9_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_9_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_9_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_9_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_9_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_10_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_10_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_10_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_10_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_10_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_10_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_10_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_10_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_10_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_10_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_10_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_10_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_10_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_10_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_10_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_10_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_10_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_10_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_10_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_10_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_10_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_10_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_10_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_11_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_11_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_11_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_11_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_11_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_11_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_11_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_11_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_11_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_11_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_11_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_11_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_11_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_11_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_11_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_11_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_11_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_11_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_11_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_11_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_11_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_11_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_11_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_12_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_12_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_12_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_12_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_12_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_12_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_12_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_12_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_12_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_12_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_12_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_12_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_12_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_12_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_12_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_12_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_12_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_12_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_12_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_12_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_12_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_12_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_12_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_13_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_13_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_13_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_13_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_13_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_13_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_13_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_13_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_13_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_13_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_13_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_13_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_13_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_13_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_13_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_13_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_13_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_13_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_13_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_13_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_13_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_13_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_13_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_14_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_14_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_14_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_14_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_14_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_14_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_14_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_14_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_14_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_14_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_14_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_14_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_14_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_14_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_14_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_14_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_14_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_14_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_14_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_14_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_14_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_14_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_14_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_15_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQCQ_DRCT_SEL_15_OFFSET          24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_ERR_DONE_INT_EN_15_OFFSET 23
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_15_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_ERR_DONE_INT_EN_15_OFFSET  22
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_15_LEN               2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_TIME_15_OFFSET            20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_15_LEN                 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_MRG_EN_15_OFFSET              19
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_15_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_REMOTE_SUBCMD_RO_EN_15_OFFSET    18
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_15_LEN          1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_LOCAL_4K_WAIT_EN_15_OFFSET       16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_15_LEN                8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ARB_WEIGHT_15_OFFSET             8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_15_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_PAUSE_15_OFFSET                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_15_LEN              1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ABORT_EN_15_OFFSET           2
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_15_LEN                     1
#define HIPCIEC_AP_DMA_REG_DMA_EP_PORT_SEL_15_OFFSET                  1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_15_LEN                        1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_EN_15_OFFSET                     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_0_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_0_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_0_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_1_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_1_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_1_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_2_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_2_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_2_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_3_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_3_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_3_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_4_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_4_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_4_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_5_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_5_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_5_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_6_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_6_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_6_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_7_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_7_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_7_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_8_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_8_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_8_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_9_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_9_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_9_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_10_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_10_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_10_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_11_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_11_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_11_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_12_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_12_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_12_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_13_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_13_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_13_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_14_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_14_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_14_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ABORT_EXIT_15_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_15_LEN         1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESET_15_OFFSET      0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RSV_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_0_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_0_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_0_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_0_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_0_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_0_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_0_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_1_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_1_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_1_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_1_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_1_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_1_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_1_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_2_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_2_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_2_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_2_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_2_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_2_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_2_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_3_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_3_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_3_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_3_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_3_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_3_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_3_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_4_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_4_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_4_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_4_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_4_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_4_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_4_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_5_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_5_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_5_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_5_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_5_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_5_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_5_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_6_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_6_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_6_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_6_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_6_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_6_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_6_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_7_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_7_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_7_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_7_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_7_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_7_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_7_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_8_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_8_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_8_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_8_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_8_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_8_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_8_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_9_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_9_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_9_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_9_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_9_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_9_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_9_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_10_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_10_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_10_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_10_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_10_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_10_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_10_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_11_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_11_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_11_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_11_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_11_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_11_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_11_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_12_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_12_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_12_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_12_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_12_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_12_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_12_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_13_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_13_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_13_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_13_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_13_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_13_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_13_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_14_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_14_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_14_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_14_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_14_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_14_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_14_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_15_LEN          3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SUB_FSM_STS_15_OFFSET       8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_WAIT_SPD_DATA_STS_15_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_15_LEN             1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_NOT_WORK_15_OFFSET          4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_15_LEN                  4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_15_OFFSET               0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_0_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_0_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_0_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_0_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_0_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_0_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_0_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_0_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_0_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_1_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_1_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_1_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_1_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_1_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_1_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_1_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_1_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_1_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_2_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_2_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_2_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_2_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_2_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_2_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_2_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_2_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_2_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_3_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_3_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_3_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_3_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_3_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_3_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_3_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_3_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_3_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_4_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_4_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_4_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_4_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_4_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_4_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_4_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_4_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_4_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_5_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_5_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_5_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_5_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_5_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_5_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_5_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_5_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_5_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_6_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_6_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_6_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_6_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_6_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_6_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_6_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_6_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_6_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_7_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_7_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_7_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_7_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_7_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_7_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_7_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_7_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_7_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_8_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_8_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_8_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_8_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_8_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_8_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_8_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_8_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_8_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_9_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_9_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_9_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_9_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_9_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_9_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_9_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_9_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_9_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_10_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_10_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_10_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_10_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_10_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_10_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_10_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_10_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_10_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_11_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_11_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_11_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_11_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_11_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_11_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_11_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_11_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_11_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_12_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_12_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_12_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_12_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_12_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_12_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_12_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_12_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_12_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_13_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_13_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_13_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_13_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_13_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_13_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_13_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_13_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_13_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_14_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_14_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_14_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_14_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_14_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_14_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_14_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_14_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_14_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_15_LEN        7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_SEND_CNT_15_OFFSET     25
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RESP_REC_FINISH_15_OFFSET 24
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_15_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_TAG_VLD_15_OFFSET      20
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_15_LEN         4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PRE_NUM_15_OFFSET      16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_15_LEN        16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_HEAD_PTR_15_OFFSET     0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_BYTE_CNT_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CQ_TAIL_PTR_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_0_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_0_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_0_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_0_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_0_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_0_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_0_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_0_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_0_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_0_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_0_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_0_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_0_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_0_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_1_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_1_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_1_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_1_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_1_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_1_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_1_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_1_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_1_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_1_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_1_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_1_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_1_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_1_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_2_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_2_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_2_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_2_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_2_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_2_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_2_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_2_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_2_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_2_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_2_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_2_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_2_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_2_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_3_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_3_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_3_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_3_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_3_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_3_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_3_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_3_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_3_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_3_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_3_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_3_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_3_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_3_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_4_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_4_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_4_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_4_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_4_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_4_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_4_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_4_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_4_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_4_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_4_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_4_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_4_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_4_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_5_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_5_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_5_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_5_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_5_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_5_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_5_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_5_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_5_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_5_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_5_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_5_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_5_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_5_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_6_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_6_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_6_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_6_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_6_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_6_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_6_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_6_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_6_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_6_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_6_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_6_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_6_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_6_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_7_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_7_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_7_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_7_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_7_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_7_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_7_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_7_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_7_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_7_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_7_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_7_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_7_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_7_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_8_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_8_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_8_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_8_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_8_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_8_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_8_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_8_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_8_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_8_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_8_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_8_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_8_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_8_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_9_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_9_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_9_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_9_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_9_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_9_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_9_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_9_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_9_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_9_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_9_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_9_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_9_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_9_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_10_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_10_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_10_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_10_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_10_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_10_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_10_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_10_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_10_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_10_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_10_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_10_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_10_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_10_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_11_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_11_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_11_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_11_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_11_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_11_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_11_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_11_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_11_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_11_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_11_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_11_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_11_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_11_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_12_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_12_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_12_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_12_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_12_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_12_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_12_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_12_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_12_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_12_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_12_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_12_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_12_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_12_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_13_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_13_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_13_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_13_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_13_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_13_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_13_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_13_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_13_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_13_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_13_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_13_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_13_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_13_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_14_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_14_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_14_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_14_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_14_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_14_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_14_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_14_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_14_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_14_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_14_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_14_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_14_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_14_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_STS_15_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_STS_15_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_STS_15_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_STS_15_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_STS_15_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_STS_15_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_STS_15_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_STS_15_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_STS_15_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_STS_15_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_STS_15_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_STS_15_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_15_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_STS_15_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_0_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_0_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_0_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_0_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_0_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_0_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_0_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_0_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_0_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_0_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_0_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_0_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_0_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_0_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_1_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_1_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_1_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_1_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_1_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_1_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_1_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_1_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_1_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_1_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_1_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_1_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_1_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_1_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_2_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_2_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_2_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_2_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_2_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_2_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_2_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_2_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_2_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_2_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_2_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_2_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_2_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_2_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_3_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_3_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_3_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_3_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_3_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_3_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_3_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_3_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_3_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_3_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_3_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_3_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_3_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_3_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_4_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_4_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_4_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_4_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_4_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_4_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_4_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_4_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_4_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_4_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_4_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_4_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_4_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_4_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_5_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_5_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_5_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_5_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_5_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_5_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_5_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_5_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_5_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_5_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_5_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_5_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_5_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_5_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_6_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_6_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_6_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_6_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_6_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_6_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_6_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_6_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_6_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_6_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_6_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_6_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_6_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_6_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_7_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_7_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_7_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_7_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_7_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_7_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_7_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_7_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_7_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_7_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_7_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_7_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_7_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_7_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_8_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_8_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_8_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_8_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_8_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_8_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_8_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_8_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_8_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_8_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_8_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_8_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_8_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_8_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_9_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_9_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_9_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_9_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_9_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_9_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_9_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_9_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_9_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_9_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_9_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_9_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_9_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_9_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_10_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_10_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_10_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_10_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_10_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_10_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_10_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_10_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_10_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_10_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_10_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_10_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_10_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_10_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_11_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_11_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_11_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_11_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_11_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_11_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_11_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_11_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_11_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_11_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_11_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_11_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_11_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_11_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_12_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_12_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_12_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_12_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_12_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_12_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_12_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_12_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_12_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_12_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_12_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_12_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_12_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_12_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_13_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_13_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_13_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_13_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_13_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_13_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_13_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_13_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_13_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_13_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_13_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_13_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_13_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_13_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_14_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_14_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_14_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_14_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_14_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_14_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_14_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_14_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_14_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_14_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_14_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_14_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_14_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_14_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_MSK_15_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_MSK_15_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_MSK_15_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_MSK_15_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_MSK_15_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_MSK_15_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_MSK_15_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_MSK_15_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_MSK_15_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_MSK_15_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_MSK_15_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_MSK_15_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_15_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_MSK_15_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_0_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_1_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_2_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_3_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_L_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR_ADDR_H_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_SQ_PTR_ERR_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_0_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_0_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_0_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_0_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_0_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_0_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_0_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_0_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_0_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_0_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_0_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_0_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_0_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_0_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_1_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_1_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_1_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_1_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_1_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_1_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_1_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_1_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_1_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_1_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_1_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_1_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_1_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_1_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_2_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_2_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_2_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_2_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_2_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_2_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_2_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_2_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_2_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_2_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_2_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_2_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_2_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_2_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_3_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_3_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_3_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_3_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_3_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_3_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_3_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_3_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_3_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_3_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_3_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_3_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_3_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_3_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_4_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_4_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_4_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_4_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_4_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_4_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_4_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_4_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_4_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_4_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_4_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_4_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_4_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_4_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_5_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_5_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_5_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_5_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_5_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_5_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_5_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_5_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_5_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_5_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_5_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_5_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_5_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_5_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_6_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_6_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_6_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_6_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_6_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_6_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_6_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_6_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_6_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_6_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_6_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_6_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_6_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_6_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_7_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_7_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_7_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_7_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_7_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_7_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_7_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_7_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_7_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_7_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_7_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_7_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_7_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_7_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_8_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_8_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_8_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_8_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_8_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_8_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_8_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_8_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_8_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_8_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_8_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_8_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_8_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_8_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_9_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_9_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_9_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_9_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_9_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_9_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_9_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_9_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_9_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_9_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_9_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_9_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_9_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_9_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_10_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_10_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_10_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_10_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_10_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_10_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_10_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_10_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_10_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_10_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_10_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_10_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_10_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_10_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_11_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_11_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_11_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_11_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_11_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_11_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_11_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_11_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_11_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_11_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_11_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_11_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_11_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_11_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_12_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_12_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_12_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_12_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_12_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_12_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_12_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_12_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_12_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_12_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_12_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_12_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_12_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_12_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_13_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_13_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_13_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_13_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_13_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_13_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_13_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_13_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_13_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_13_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_13_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_13_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_13_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_13_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_14_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_14_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_14_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_14_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_14_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_14_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_14_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_14_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_14_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_14_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_14_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_14_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_14_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_14_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR11_15_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR10_15_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR09_15_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR08_15_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR07_15_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR06_15_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR05_15_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR04_15_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR03_15_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR02_15_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR01_15_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_ERR00_15_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_15_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_STS_DONE_15_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_0_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_0_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_0_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_0_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_0_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_0_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_0_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_0_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_0_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_0_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_0_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_0_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_0_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_0_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_0_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_1_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_1_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_1_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_1_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_1_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_1_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_1_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_1_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_1_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_1_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_1_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_1_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_1_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_1_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_1_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_2_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_2_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_2_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_2_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_2_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_2_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_2_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_2_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_2_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_2_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_2_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_2_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_2_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_2_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_2_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_3_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_3_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_3_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_3_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_3_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_3_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_3_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_3_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_3_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_3_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_3_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_3_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_3_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_3_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_3_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_4_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_4_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_4_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_4_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_4_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_4_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_4_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_4_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_4_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_4_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_4_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_4_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_4_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_4_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_4_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_5_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_5_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_5_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_5_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_5_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_5_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_5_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_5_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_5_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_5_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_5_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_5_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_5_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_5_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_5_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_6_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_6_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_6_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_6_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_6_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_6_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_6_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_6_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_6_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_6_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_6_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_6_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_6_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_6_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_6_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_7_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_7_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_7_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_7_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_7_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_7_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_7_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_7_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_7_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_7_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_7_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_7_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_7_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_7_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_7_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_8_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_8_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_8_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_8_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_8_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_8_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_8_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_8_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_8_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_8_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_8_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_8_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_8_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_8_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_8_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_9_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_9_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_9_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_9_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_9_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_9_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_9_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_9_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_9_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_9_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_9_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_9_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_9_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_9_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_9_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_10_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_10_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_10_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_10_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_10_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_10_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_10_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_10_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_10_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_10_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_10_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_10_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_10_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_10_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_10_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_11_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_11_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_11_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_11_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_11_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_11_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_11_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_11_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_11_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_11_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_11_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_11_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_11_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_11_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_11_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_12_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_12_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_12_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_12_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_12_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_12_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_12_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_12_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_12_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_12_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_12_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_12_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_12_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_12_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_12_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_13_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_13_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_13_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_13_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_13_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_13_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_13_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_13_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_13_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_13_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_13_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_13_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_13_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_13_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_13_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_14_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_14_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_14_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_14_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_14_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_14_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_14_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_14_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_14_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_14_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_14_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_14_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_14_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_14_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_14_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_INT_SET_15_OFFSET 12
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_INT_SET_15_OFFSET 11
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_INT_SET_15_OFFSET 10
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_INT_SET_15_OFFSET 9
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_INT_SET_15_OFFSET 8
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_INT_SET_15_OFFSET 7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_INT_SET_15_OFFSET 6
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_INT_SET_15_OFFSET 5
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_INT_SET_15_OFFSET 4
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_INT_SET_15_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_INT_SET_15_OFFSET 2
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_15_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_INT_SET_15_OFFSET 1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_15_LEN     1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_DONE_INT_SET_15_OFFSET  0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_4_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_5_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_6_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_0_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_1_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_2_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_3_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_4_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_5_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_6_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_7_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_8_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_9_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_10_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_11_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_12_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_13_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_14_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_15_LEN    32
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_CURR_DESP_7_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_0_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_1_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_2_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_3_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_4_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_5_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_6_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_7_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_8_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_9_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_10_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_11_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_12_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_13_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_14_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR01_NUM_15_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR00_NUM_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_0_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_1_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_2_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_3_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_4_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_5_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_6_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_7_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_8_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_9_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_10_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_11_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_12_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_13_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_14_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR02_NUM_15_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR03_NUM_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_0_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_1_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_2_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_3_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_4_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_5_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_6_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_7_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_8_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_9_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_10_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_11_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_12_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_13_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_14_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR04_NUM_15_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR05_NUM_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_0_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_1_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_2_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_3_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_4_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_5_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_6_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_7_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_8_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_9_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_10_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_11_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_12_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_13_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_14_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR06_NUM_15_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR07_NUM_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_0_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_1_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_2_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_3_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_4_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_5_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_6_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_7_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_8_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_9_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_10_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_11_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_12_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_13_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_14_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR08_NUM_15_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR09_NUM_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_0_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_1_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_2_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_3_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_4_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_5_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_6_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_7_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_8_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_9_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_10_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_11_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_12_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_13_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_14_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR10_NUM_15_OFFSET 16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_ERR11_NUM_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_0_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_0_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_0_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_1_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_1_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_1_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_2_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_2_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_2_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_3_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_3_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_3_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_4_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_4_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_4_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_5_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_5_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_5_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_6_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_6_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_6_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_7_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_7_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_7_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_8_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_8_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_8_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_9_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_9_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_9_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_10_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_10_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_10_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_11_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_11_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_11_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_12_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_12_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_12_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_13_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_13_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_13_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_14_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_14_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_14_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_15_LEN    7
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_VF_CFG_15_OFFSET 3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_15_LEN    3
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_RMT_PF_CFG_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_0_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_0_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_0_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_1_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_1_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_1_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_2_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_2_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_2_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_3_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_3_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_3_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_4_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_4_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_4_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_5_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_5_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_5_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_6_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_6_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_6_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_7_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_7_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_7_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_8_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_8_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_8_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_8_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_9_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_9_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_9_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_9_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_10_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_10_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_10_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_10_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_11_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_11_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_11_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_11_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_12_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_12_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_12_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_12_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_13_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_13_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_13_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_13_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_14_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_14_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_14_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_14_OFFSET 0

#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_15_LEN       1
#define HIPCIEC_AP_DMA_REG_DMA_DONE_INT_MERGE_EN_15_OFFSET    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_15_LEN    16
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE_INT_MERGE_TIME_15_OFFSET 0

#define HIPCIEC_AP_DMA_REG_ECC_2BIT_INJECT_LEN    1
#define HIPCIEC_AP_DMA_REG_ECC_2BIT_INJECT_OFFSET 1
#define HIPCIEC_AP_DMA_REG_ECC_1BIT_INJECT_LEN    1
#define HIPCIEC_AP_DMA_REG_ECC_1BIT_INJECT_OFFSET 0

#define HIPCIEC_AP_DMA_REG_ECC_2BIT_ERR_ADDR_LEN    16
#define HIPCIEC_AP_DMA_REG_ECC_2BIT_ERR_ADDR_OFFSET 16
#define HIPCIEC_AP_DMA_REG_ECC_1BIT_ERR_ADDR_LEN    16
#define HIPCIEC_AP_DMA_REG_ECC_1BIT_ERR_ADDR_OFFSET 0

#define HIPCIEC_AP_DMA_REG_ECC_2BIT_CNT_LEN     16
#define HIPCIEC_AP_DMA_REG_ECC_2BIT_CNT_OFFSET  16
#define HIPCIEC_AP_DMA_REG_ECC_1BIT_CNTR_LEN    16
#define HIPCIEC_AP_DMA_REG_ECC_1BIT_CNTR_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_TAG_ERR_INT_MSK_LEN    1
#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_TAG_ERR_INT_MSK_OFFSET 5
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_TAG_ERR_INT_MSK_LEN     1
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_TAG_ERR_INT_MSK_OFFSET  4
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_TAG_ERR_INT_MSK_LEN    1
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_TAG_ERR_INT_MSK_OFFSET 3
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_TAG_ERR_INT_MSK_LEN     1
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_TAG_ERR_INT_MSK_OFFSET  2
#define HIPCIEC_AP_DMA_REG_ECC_2BIT_ERR_INT_MSK_LEN              1
#define HIPCIEC_AP_DMA_REG_ECC_2BIT_ERR_INT_MSK_OFFSET           1
#define HIPCIEC_AP_DMA_REG_ECC_1BIT_ERR_INT_MSK_LEN              1
#define HIPCIEC_AP_DMA_REG_ECC_1BIT_ERR_INT_MSK_OFFSET           0

#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_TAG_ERR_INT_LEN    1
#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_TAG_ERR_INT_OFFSET 5
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_TAG_ERR_INT_LEN     1
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_TAG_ERR_INT_OFFSET  4
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_TAG_ERR_INT_LEN    1
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_TAG_ERR_INT_OFFSET 3
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_TAG_ERR_INT_LEN     1
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_TAG_ERR_INT_OFFSET  2
#define HIPCIEC_AP_DMA_REG_ECC_2BIT_ERR_INT_LEN              1
#define HIPCIEC_AP_DMA_REG_ECC_2BIT_ERR_INT_OFFSET           1
#define HIPCIEC_AP_DMA_REG_ECC_1BIT_ERR_INT_LEN              1
#define HIPCIEC_AP_DMA_REG_ECC_1BIT_ERR_INT_OFFSET           0

#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_TAG_ERR_ST_LEN    1
#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_TAG_ERR_ST_OFFSET 5
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_TAG_ERR_ST_LEN     1
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_TAG_ERR_ST_OFFSET  4
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_TAG_ERR_ST_LEN    1
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_TAG_ERR_ST_OFFSET 3
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_TAG_ERR_ST_LEN     1
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_TAG_ERR_ST_OFFSET  2
#define HIPCIEC_AP_DMA_REG_ECC_2BIT_ERR_ST_LEN              1
#define HIPCIEC_AP_DMA_REG_ECC_2BIT_ERR_ST_OFFSET           1
#define HIPCIEC_AP_DMA_REG_ECC_1BIT_ERR_ST_LEN              1
#define HIPCIEC_AP_DMA_REG_ECC_1BIT_ERR_ST_OFFSET           0

#define HIPCIEC_AP_DMA_REG_DMA_QUEUE0_ERR_STS_LEN    1
#define HIPCIEC_AP_DMA_REG_DMA_QUEUE0_ERR_STS_OFFSET 1
#define HIPCIEC_AP_DMA_REG_CM_ERR_STS_LEN            1
#define HIPCIEC_AP_DMA_REG_CM_ERR_STS_OFFSET         0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_CTRL_LEN    1
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_CTRL_OFFSET 1
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_CTRL_LEN    1
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_CTRL_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_HEADER_0_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_HEADER_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_HEADER_1_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_HEADER_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_HEADER_2_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_HEADER_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_HEADER_3_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_HEADER_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_0_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_1_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_2_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_3_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_4_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_5_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_6_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_7_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_DATA_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_0_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_1_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_2_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_3_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_4_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_5_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_6_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_7_LEN    32
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_HEADER_0_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_HEADER_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_HEADER_1_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_HEADER_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_HEADER_2_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_HEADER_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_HEADER_3_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_HEADER_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_0_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_1_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_2_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_3_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_4_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_5_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_6_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_7_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_DATA_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_0_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_1_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_2_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_3_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_4_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_4_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_5_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_5_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_6_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_6_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_7_LEN    32
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_7_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_ERR_LEN    1
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_ERR_OFFSET 3
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_ERR_LEN    1
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_ERR_OFFSET 2
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_VLD_LEN    1
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_RESP_DATA_VLD_OFFSET 1
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_VLD_LEN    1
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_RESP_DATA_VLD_OFFSET 0

#define HIPCIEC_AP_DMA_REG_LOCAL_EP0_CPL_TAG_ID_STATUS_0_LEN    32
#define HIPCIEC_AP_DMA_REG_LOCAL_EP0_CPL_TAG_ID_STATUS_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_LOCAL_EP0_CPL_TAG_ID_STATUS_1_LEN    32
#define HIPCIEC_AP_DMA_REG_LOCAL_EP0_CPL_TAG_ID_STATUS_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_LOCAL_EP0_CPL_TAG_ID_STATUS_2_LEN    32
#define HIPCIEC_AP_DMA_REG_LOCAL_EP0_CPL_TAG_ID_STATUS_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_LOCAL_EP0_CPL_TAG_ID_STATUS_3_LEN    32
#define HIPCIEC_AP_DMA_REG_LOCAL_EP0_CPL_TAG_ID_STATUS_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_LOCAL_EP1_CPL_TAG_ID_STATUS_0_LEN    32
#define HIPCIEC_AP_DMA_REG_LOCAL_EP1_CPL_TAG_ID_STATUS_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_LOCAL_EP1_CPL_TAG_ID_STATUS_1_LEN    32
#define HIPCIEC_AP_DMA_REG_LOCAL_EP1_CPL_TAG_ID_STATUS_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_LOCAL_EP1_CPL_TAG_ID_STATUS_2_LEN    32
#define HIPCIEC_AP_DMA_REG_LOCAL_EP1_CPL_TAG_ID_STATUS_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_LOCAL_EP1_CPL_TAG_ID_STATUS_3_LEN    32
#define HIPCIEC_AP_DMA_REG_LOCAL_EP1_CPL_TAG_ID_STATUS_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_CPL_TAG_ID_STATUS_0_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_CPL_TAG_ID_STATUS_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_CPL_TAG_ID_STATUS_1_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_CPL_TAG_ID_STATUS_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_CPL_TAG_ID_STATUS_2_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_CPL_TAG_ID_STATUS_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_CPL_TAG_ID_STATUS_3_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_CPL_TAG_ID_STATUS_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_CPL_TAG_ID_STATUS_0_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_CPL_TAG_ID_STATUS_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_CPL_TAG_ID_STATUS_1_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_CPL_TAG_ID_STATUS_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_CPL_TAG_ID_STATUS_2_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_CPL_TAG_ID_STATUS_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_CPL_TAG_ID_STATUS_3_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_CPL_TAG_ID_STATUS_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_P_TAG_ID_STATUS_0_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_P_TAG_ID_STATUS_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_P_TAG_ID_STATUS_1_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_P_TAG_ID_STATUS_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_P_TAG_ID_STATUS_2_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_P_TAG_ID_STATUS_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_P_TAG_ID_STATUS_3_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP0_P_TAG_ID_STATUS_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_P_TAG_ID_STATUS_0_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_P_TAG_ID_STATUS_0_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_P_TAG_ID_STATUS_1_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_P_TAG_ID_STATUS_1_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_P_TAG_ID_STATUS_2_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_P_TAG_ID_STATUS_2_OFFSET 0

#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_P_TAG_ID_STATUS_3_LEN    32
#define HIPCIEC_AP_DMA_REG_REMOTE_EP1_P_TAG_ID_STATUS_3_OFFSET 0

#define HIPCIEC_AP_DMA_REG_LOCAL_EP1_TLP_P_PH_CFG_LEN    2
#define HIPCIEC_AP_DMA_REG_LOCAL_EP1_TLP_P_PH_CFG_OFFSET 18
#define HIPCIEC_AP_DMA_REG_LOCAL_EP0_TLP_P_PH_CFG_LEN    2
#define HIPCIEC_AP_DMA_REG_LOCAL_EP0_TLP_P_PH_CFG_OFFSET 16
#define HIPCIEC_AP_DMA_REG_LOCAL_EP1_TLP_P_ST_CFG_LEN    8
#define HIPCIEC_AP_DMA_REG_LOCAL_EP1_TLP_P_ST_CFG_OFFSET 8
#define HIPCIEC_AP_DMA_REG_LOCAL_EP0_TLP_P_ST_CFG_LEN    8
#define HIPCIEC_AP_DMA_REG_LOCAL_EP0_TLP_P_ST_CFG_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_PRFX_DWEN_LEN    1
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_PRFX_DWEN_OFFSET 22
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_PRFX_PMR_LEN     1
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_PRFX_PMR_OFFSET  21
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_PRFX_ER_LEN      1
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_PRFX_ER_OFFSET   20
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_PASID_LEN        20
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_PASID_OFFSET     0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_PRFX_DWEN_LEN    1
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_PRFX_DWEN_OFFSET 22
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_PRFX_PMR_LEN     1
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_PRFX_PMR_OFFSET  21
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_PRFX_ER_LEN      1
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_PRFX_ER_OFFSET   20
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_PASID_LEN        20
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_PASID_OFFSET     0

#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_PF_LEN    3
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_PF_OFFSET 19
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_VF_LEN    8
#define HIPCIEC_AP_DMA_REG_EP1_ATOMIC_VF_OFFSET 11
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_PF_LEN    3
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_PF_OFFSET 8
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_VF_LEN    8
#define HIPCIEC_AP_DMA_REG_EP0_ATOMIC_VF_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP1_STS_IDLE_LEN    1
#define HIPCIEC_AP_DMA_REG_EP1_STS_IDLE_OFFSET 1
#define HIPCIEC_AP_DMA_REG_EP0_STS_IDLE_LEN    1
#define HIPCIEC_AP_DMA_REG_EP0_STS_IDLE_OFFSET 0

#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_NP_CNT_LEN    16
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_NP_CNT_OFFSET 16
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_P_CNT_LEN     16
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_P_CNT_OFFSET  0

#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_NP_CNT_LEN    16
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_NP_CNT_OFFSET 16
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_P_CNT_LEN     16
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_P_CNT_OFFSET  0

#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_NP_CNT_LEN    16
#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_NP_CNT_OFFSET 16
#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_P_CNT_LEN     16
#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_P_CNT_OFFSET  0

#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_NP_CNT_LEN    16
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_NP_CNT_OFFSET 16
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_P_CNT_LEN     16
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_P_CNT_OFFSET  0

#define HIPCIEC_AP_DMA_REG_SQ_NP_CNT_LEN    16
#define HIPCIEC_AP_DMA_REG_SQ_NP_CNT_OFFSET 16
#define HIPCIEC_AP_DMA_REG_CQ_P_CNT_LEN     16
#define HIPCIEC_AP_DMA_REG_CQ_P_CNT_OFFSET  0

#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_CNT_LEN    16
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_CNT_OFFSET 16
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_CNT_LEN     16
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_CNT_OFFSET  0

#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_CNT_LEN    16
#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_CNT_OFFSET 16
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_CNT_LEN     16
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_CNT_OFFSET  0

#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_NP_BKPR_LEN     1
#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_NP_BKPR_OFFSET  14
#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_P_BKPR_LEN      1
#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_P_BKPR_OFFSET   13
#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_BKPR_LEN    1
#define HIPCIEC_AP_DMA_REG_EP1_REMOTE_CPL_BKPR_OFFSET 12
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_NP_BKPR_LEN      1
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_NP_BKPR_OFFSET   11
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_P_BKPR_LEN       1
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_P_BKPR_OFFSET    10
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_BKPR_LEN     1
#define HIPCIEC_AP_DMA_REG_EP1_LOCAL_CPL_BKPR_OFFSET  9
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_NP_BKPR_LEN     1
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_NP_BKPR_OFFSET  8
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_P_BKPR_LEN      1
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_P_BKPR_OFFSET   7
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_BKPR_LEN    1
#define HIPCIEC_AP_DMA_REG_EP0_REMOTE_CPL_BKPR_OFFSET 6
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_NP_BKPR_LEN      1
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_NP_BKPR_OFFSET   5
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_P_BKPR_LEN       1
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_P_BKPR_OFFSET    4
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_BKPR_LEN     1
#define HIPCIEC_AP_DMA_REG_EP0_LOCAL_CPL_BKPR_OFFSET  3
#define HIPCIEC_AP_DMA_REG_SQ_NP_BKPR_LEN             1
#define HIPCIEC_AP_DMA_REG_SQ_NP_BKPR_OFFSET          2
#define HIPCIEC_AP_DMA_REG_SQ_CPL_BKPR_LEN            1
#define HIPCIEC_AP_DMA_REG_SQ_CPL_BKPR_OFFSET         1
#define HIPCIEC_AP_DMA_REG_CQ_P_BKPR_LEN              1
#define HIPCIEC_AP_DMA_REG_CQ_P_BKPR_OFFSET           0

#define HIPCIEC_AP_DMA_REG_EP1_LINKDOWN_CNT_LEN    8
#define HIPCIEC_AP_DMA_REG_EP1_LINKDOWN_CNT_OFFSET 8
#define HIPCIEC_AP_DMA_REG_EP0_LINKDOWN_CNT_LEN    8
#define HIPCIEC_AP_DMA_REG_EP0_LINKDOWN_CNT_OFFSET 0

#endif // __HIPCIEC_AP_DMA_REG_REG_OFFSET_FIELD_H__
